SILICON G FIFTY SEVEN

Brand	Owner (click to sort)	Address	Description
SILICON G57	Glycan Industries	5405 Alton Parkway Suite A313 Irvine CA 92604	SILICON G FIFTY SEVEN;Cosmetic creams, cosmetic oils, cosmetic soaps, gels, lotions, and topical skin sprays; cosmetics, namely, non-medicated lotions, sprays, gels and creams with silicon and boron content in order to protect astronauts from solar and cosmic radiations sources; non-medicated hair restoration lotions; lotions for hair; Tooth paste; Tooth gel; all the foregoing containing silicon as an ingredient;SILICON;
SILICON G57	Glycan Industries	5405 Alton Parkway Suite A313 Irvine CA 92604	SILICON G FIFTY SEVEN; SILICON GLYCAN FIFTY SEVEN;Aerated water; Beer; Fruit drinks and fruit juices; Mineral water; Soft drinks; Soft drinks, namely, sodas; Beers; Mineral water; Syrups for making beverages; all the foregoing containing silicon as an ingredient;SILICON;
SILICON G57	Glycan Industries	5405 Alton Parkway Suite A313 Irvine CA 92604	SILICON G FIFTY SEVEN;Chemical additives for use in the manufacture of cosmetics; Chemical additives for use in the manufacture of food; Chemical additives for use in the manufacture of pharmaceuticals; Chemical additives for use in the manufacture of food, pharmaceuticals, cosmetics, animal feed,alcoholic beverages, non alcoholic beverages; Specialty chemicals, namely, chemical additives for general industrial use in the manufacture of a wide variety of goods;SILICON;
	Where the owner name is not linked, that owner no longer owns the brand

Technical Examples

Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.