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TEA CEREMONY INSTRUCTION
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Technical Examples
- A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent of the first instruction.
- A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
- Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
- A REPEAT instruction for repeated execution of an associated instruction (INSTR). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the associated instruction (INSTR) has been executed the number of times indicated by a COUNT value in a preloaded register, or alternatively, by the REPEAT instruction itself. In this manner, the present invention reduces the number of instruction fetches required to repeatedly execute the associated instruction (INSTR). Consequently, there is a significant improvement in the efficiency of the program code execution.
- The present invention provides a processor with an instruction memory hierarchy and a method for distributing instructions to an array of multithreaded processing units organized in processor clusters. The instruction memory hierarchy comprises a processor cluster, an instruction request bus, an instruction request arbiter, and an instruction memory. The instruction request arbiter controls submissions of instruction requests from multithreaded processing units within the processor clusters to the instruction memory. The processor clusters send instruction requests responsive to a cache miss by a processor, or processor thread, within the processor cluster. The instruction request arbiter resolves conflicts between instruction requests attempting to access to a common cache set within the instruction memory. The instruction memory broadcasts instruction data to the processor clusters responsive to non-conflicting instruction requests forwarded from the instruction request arbiter.
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