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SIGNAL MODE CONNECTORS

Brand Owner
ABRITRONIX Abitronix LLC
Technical Examples
  1. The present invention relates to methods and systems for minimizing alien crosstalk between connectors. Specifically, the methods and systems relate to isolation and compensation techniques for minimizing alien crosstalk between connectors for use with high-speed data cabling. A frame can be configured to receive a number of connectors. Shield structures may be positioned to isolate at least a subset of the connectors from one another. The connectors can be positioned to move at least a subset of the connectors away from alignment with a common plane. A signal compensator may be configured to adjust a data signal to compensate for alien crosstalk. The connectors are configured to efficiently and accurately propagate high-speed data signals by, among other functions, minimizing alien crosstalk.
  2. An on die termination (ODT) mode transfer circuit, for use in a semiconductor memory device, including: a delay locked loop (DLL) for receiving an external clock signal in order to generate a DLL clock signal according to a power down mode and an active-standby mode; an ODT mode signal generation means for generating an ODT mode signal in response to the DLL clock signal and a clock enable signal; and an ODT control means for generating a termination resistor (RTT) signal in response to an ODT signal and the ODT mode signal.
  3. Techniques where PCIe is implemented using connectors that are compatable with Cardbus/MPCI connectors. One technique implements PCIe on unused pins on Cardbus/MPCI connectors. An advantage of this implementation is that it provides a single, smaller connection point than utilizing separate connectors. Another technique is to add additional pins to a PCI connector for processing PCIe low voltage differential signal pairs. Although this technique is not as small as the first technique, it is still smaller than utilizing separate connectors.
  4. An insulation displacement contact (IDC) includes: upper and lower ends, each of the upper and lower ends including a slot configured to receive a conductor therein, the slots being generally parallel and non-collinear; and a transitional area merging with the upper and lower ends. An IDC of this configuration can be employed, for example, in 110-style connectors, and can enable such connectors to compensate for differential to common mode crosstalk between adjacent IDC pairs.
  5. An apparatus for automatically selecting one of a standard decision directed mode and a soft dd mode in a decision feedback equalizer for receiving a data signal includes an equalizer utilizing forward error correction for providing first and second output signals corresponding to a DFE automatic switching mode and a soft automatic switching mode, respectively, and a comparator for comparing byte error rates of the first and second output signals for selecting as a superior mode that mode associated with a lower ByER and outputting the output signal with the lower ByER. A lock detector provides a lock signal derived from the DFE output signal with the lower ByER and a mode switch selectively places the DFE outputs in one of the dd modes or a blind mode, depending on the lock signal.

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