MATERIAL TREATMENT SUBSTRATES USED

Brand Owner Address Description
PACTECH MEMBER OF NAGASE GROUP Pac Tech - Packaging Technologies GmbH Am Schlangenhorst 7 - 9 14641 Nauen Germany Material treatment of substrates used in the field of microelectronics, in particular semiconductor substrates and flexible substrates;The mark consists of the following: a red circle containing a grid of red squares and the letters PT formed by white squares, the wording PACTECH in blue and outlined in black, and the wording MEMBER OF NAGASE GROUP in red.;Mechanical apparatuses, in particular automatic machines, with regard to microperipheric technologies, namely, semiconductor wafer processing machines; mechanical apparatuses, in particular automatic machines, for the application of connecting materials on substrates; mechanical apparatuses, in particular automatic machines, for manufacturing microconnections, in particular for the production of substrate units from one or more substrates joined as one module, in particular chips;Contact metalizations for microconnections made from soldering material, included in class 6, namely, soldering wire of metal for microconnections;PAC TECH MEMBER OF NAGASE GROUP;The color(s) red, blue, white and black is/are claimed as a feature of the mark.;MEMBER AND GROUP;[ Development of contact metallizations for connection systems, namely, new product development for others regarding contact metallization; development of connection systems for manufacturing microconnections, namely, development of new technology for others in the field of computer systems for microconnection manufacturing; technology consulting services, in particular with regard to manufacturing microconnections, namely, consulting services in the field of designing of machines for manufacturing microconnections and in the field of development of new technology regarding microconnection manufacturing and applicability ];
 

Where the owner name is not linked, that owner no longer owns the brand

    
Technical Examples
  1. The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.